1. Field
Example embodiments are directed to a semiconductor memory device, for example, an input circuit and an output circuit of a semiconductor memory device and a method of inputting/outputting data in a semiconductor memory device.
2. Description of Related Art
A memory device may generally refer to a device for storing data and commands, temporarily or permanently, so the stored data may be used in a computer, a communication system or an image processing system, for example. Recently, semiconductor memory devices have become a widely used memory device among various types of memory devices, including semiconductor devices, a magnetic tape, magnetic disks, optical devices, etc.
Semiconductor memory devices may include Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), Flash Memory and Read Only Memory (ROM), which may be classified according to types of storing data. Storage capacity and operating speed of semiconductor memory devices have also been increasing.
DRAM devices may be classified into Single Data Rate (SDR) DRAM, Double Rata Rate (DDR) DRAM, DDR3 DRAM and Graphic DDR3 (GDDR4) according to a pre-fetch mode. SDR DRAM may pre-fetch one-bit data and process the pre-fetched one-bit data. DDR DRAM may pre-fetch two-bit data and simultaneously process the pre-fetched two-bit data. DDR3 DRAM may pre-fetch four-bit data and simultaneously process the pre-fetched four-bit data. GDDR4 DRAM may pre-fetch eight-bit data and simultaneously process the pre-fetched eight-bit data. DRAM devices may simultaneously process more bits of data as the operating speed increases.
In a semiconductor memory device having a multi-bit pre-fetch scheme, internal circuit blocks may increase as the number of bits for pre-fetching increases.
FIGS. 1-4 are diagrams schematically illustrating output paths and operation timings of a conventional semiconductor device.
Referring to FIG. 1 and FIG. 3, eight-bit data corresponding to output data of an input/output sense amplifier may be transmitted to input/output pin DQj through eight output lines (GIO). An output path of the conventional semiconductor memory device in FIG. 1 may include a buffer operating in response to a control signal PO and a multiplexer operating in response to a pre-fetch address signal. A semiconductor memory device having an X32 data input/output structure may require 256 output lines. As the number of output lines increases, the number of circuits coupled to the output lines may similarly increase.
Referring to FIG. 2 and FIG. 4, the semiconductor memory device may include clocked latches operating in response to clock signals P0 and P1 in an output terminal of the input/output sense amplifier. The semiconductor memory device may also include four output lines (GIO), whereby the semiconductor memory device may output four-bit data based on eight-bit data in response to a clock signal P0, and output the other four-bit data based on the eight-bit data in response to another clock signal P1. The output circuit in FIG. 2 may include multiplexers operating in response to pre-fetch address signals and clocked latches operating in response to control signals P0 and P1 having different phases from each other. Thus, the output circuit of the semiconductor memory device in FIG. 2 may output the first four-bit data based on the eight-bit data, and then output the other four-bit data based on the eight-bit data in response to clock signals having different phases.
A method of outputting data of the semiconductor memory device in FIG. 2, however, may require complex multiplexers and complex clock signal processing for generating eight-bit data through two output lines. In addition, a method of outputting data of the semiconductor memory device in FIG. 2 may require complex multiplexers and complex clock signal processing for generating sixteen-bit data through four output lines.